Power Estimation of System-Level Buses for Microprocessor-Based Architectures: A Case Study

The processor-to-memory communication on systemlevel buses dissipates a significant amount of the overall power in microprocessor-based architectures. A methodology has been set up to evaluate the effects of both encoding schemes and multi-level cache memories on the power consumption associated with the systemlevel address and data buses of a high-end computer system based on the PowerPC604e architecture. The main goal is to evaluate how different values of cache parameters (cache size, block size, associativity, write strategy, and block replacement policy) and the introduction of bus encoding techniques, at the different levels of the memory hierarchy, affect the system-level